Altera DE2 SDRAM controller

Overview
This is a very simple controller for the Altera DE2 SDRAM chip, with a CAS latency of 3 and a fixed burst length of 2 and auto-precharge for each read/write.

The SDRAM chip is a PSC A2V64S40CTP-G7 and the datasheet can be found on the datasheet folder of the DE2 CD-ROM. The corresponding datasheet part number is IS42S16400. The memory chip capacity on my board is 8MBytes, organized as 1,048,576 x 16 bits x 4 banks. The 1MBit is organized as 256 columns x 4096 rows. This gives a row address A[11:0] and a column address A[7:0]. Note that the DE2 manual says that some boards come with a 4MBytes chip and this will require a few small changes in the addressing area of this design.

Since this is not DDR memory, the clocking and the data read/write operations are simplified and the design runs without problem at the chip nominal speed of 133.333MHz.
Design
The design is comprised of a top module which instantiates a PLL module (for clocking the user interface, the controller and the chip), a memory controller module and a test bench module.
sdram design diagram
The top module sdram is straighforward and just instantiates the other modules.

An Altera-generated PLL module is used to generate the SDRAM chip clock, the SDRAM controller clock and the system clock. The SDRAM chip clock is 133.333 MHz. The SDRAM controller clock is also 133.333 MHz, but for timing issues, its phase is advanced of 3ns. The system clock is 50MHz and it clocks both the SDRAM test bench and the wisbone interface.

The SDRAM controller sdram_controller is as simple as it can be. It has an initialization state machine that takes care of initializing the DRAM chip and a main state machine that takes care of the read/writes. No optimization is done and each command is completed before the controller will accept the next one.

The test bench sdram_rw sequentially writes all positions in memory, pauses for a while and then reads back all positions comparing them to the written value. The green LEDG1 indicates the test passed. The red LEDR0 indicates at least one of the readbacks failed.
Using the design
Use the Altera MegaWizard to generate the PLL module. Generate 3 clocks, with clk0 @ 133MHz, clk1 @ 50MHz and clk2 @ 133 MHz with a phase adjustment of -3ns.

Create a new project with all the files provided in the design. Use the pin assignments from the DE2 CD-ROM.
Design files
altera_sdram.zip